Senior Design Engineer

Salary 72000 - 84000 SGD
Number of vacancies : 1
Reference number : 9639

Employment terms
Length of employment
Employment date
Years exp required
5-8 Years
DDR-Dual Data Rate memory, VT- Threshold Voltage, WNS- Worst Negative Slack, TNS- Total Negative Slack ,P&R -Place and Route, DFM -Design For Manufacturability ,DRC- Design Rule Check, LVS- Layout Versus Schematic, ICC2- IC Compiler – 2, ERC- Electrical Rule Checks, ECO- Engineering Change Order, EDI- Encounter Design Implementation, LEC- Logical Equivalence Check, 14FF/ 16FF- 14nanometer FinFet/ 16nanometer FinFet


- DDR controller module:

  • Extremely timing critical block
  • Clock domain with 533MHz clock
  • Critical data skew balancing up to 25ps
  • Manual handling of DQS and DQ lines
  • Floorplan critical, requiring careful placement of DLLs with respect to IO pads
  • Careful planning of DQ bits logic to ensure data skew of 25ps
  • Automated flow to run VT Swaps based on WNS and TNS

- P&R:

  • Supported a complex floorplan activity to resolve congestion issues and improve routability
  • This block has 350+ memories and rectilinear shape
  • It has 42000 feedthru pins
  • Internal tool algorithms of ICC2 had to be exploited in order to bring congestion and routability under control
  • Some methodology updates were also made along with some script development to get the above automated
  • The methodology is generic so that it applies to all the blocks

- DFM:

  • Automated the flow to get dummy fill insertion – for base and metal
  • Expert in DRC and LVS at all nodes <= 28nm
  • Has worked on DRC/ LVS of nodes as low as 16nm
  • Expert in understanding complex DRCs, and interacting with Fab to get those resolved
  • Expert in understanding LVS/ ERC issues and get the design cleaned up with very low turn around time

- Timing:

  • Expert in DDR interface timing requirements
  • Expert in Tweaker and running it to generate all timing ECOs
  • Automated flow to fix the max_tran violations in EDI

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